Prinicpal Physical Design/Implementation Engineer

About Marvell

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

What You Can Expect

This position is for either our Santa Clara or Irvine locations. Being on site full-time is required. Relocation will provided.

• Architect and lead the development of next-generation physical design methodologies and automation flows for Complex SubSystems

• Provide deep technical leadership in RTL-to-GDSII implementation, including synthesis, floor planning, place and route, clock tree synthesis, and timing closure

• Hands on work on complex Subsystem hardening

• Working with Senior and Junior engineers to deliver reference floorplan, fully synthesized, timing closed Sub System partitions to SOC team

• Work with DFT team and SOC team for DFT insertion and closing timing at SOC level

• Work with RTL team to close timing, ECOs, Bug fixes etc

• Serve as a key technical advisor across multiple projects, influencing design decisions and resolving complex implementation challenges

• Collaborate with global cross-functional teams, including RTL, verification, and CAD, to ensure cohesive and optimized design execution.

• Mentor and coach senior and junior engineers, fostering technical growth and promoting best practices across the organization

• Evaluate and drive adoption of emerging EDA tools and technologies in partnership with internal CAD and external vendors

• Represent the physical design team in strategic technical discussions with internal and external stakeholders, contributing to roadmap planning and methodology evolution

What We're Looking For

• Bachelor's degree in Computer Science, Electrical Engineering or related fields and 10-15 years of related professional experience or Master's degree and/or PhD in Computer Science, Electrical Engineering or related fields with 5-10 years of experience or equivalent professional experience in lieu of a formal degree

• Domain Expertise of SoC architecture, processor cores, memory, PCIE/CXL highly preferred

• Ethernet, Security and peripheral interfaces through hands on prior experience preferred

• Experience with Large and complex design synthesis, Floor planning, Place and Route, Clock tree and Timing closure of large Subsystems

• Extensive experience in Verilog and Static Quality checks of the implemented RTL

• Experience with Memory generation highly preferred

• Experience with leading foundries and latest process nodes 2nm, 3nm, 5nm etc preferred

• Hands on experience in interpretive language such as Perl/Python

• Proven track record of delivering production-quality designs on aggressive development schedules

• Good communication skills and self-discipline contributing in a team environment

Expected Base Pay Range (USD)

The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.

Interview Integrity

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.