Next Gen CPU Power Management RTL Design Engineer

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Whetheryou'redesigning next-gen processors, enabling AI breakthroughs, orbringing leading edge products to market, every role at AMD contributes to something bigger- technologythat moves the world forward.Join us and, together, we'll advance your career.

THE ROLE:

Do you want to be at the forefront of designing the next Ryzen, Thread ripper, or EPYC CPU? Join AMD's CPU engineering team and help shape the power management technologies that enable industry-leading performance and efficiency. As CPU Power Management and Clocking Micro-architect, you will play a key role in defining and developing the clocking, reset, and power management IP that powers AMD's next-generation processors. This is a highly collaborative role where you will work closely with architecture, design, verification, physical design, firmware, and silicon teams to deliver innovative solutions that directly impact AMD's flagship products. This role offers the opportunity to work on cutting-edge process technologies, influence critical architectural decisions, and solve complex hardware and firmware challenges. You will gain exposure to the full product lifecycle, from microarchitecture definition and RTL development through silicon bring-up and product

THE PERSON:

The ideal candidate is a highly motivated and creative engineer who enjoys solving complex technical problems and thrives in a collaborative, fast-paced environment. They are passionate about processor architecture, low-power design, and hardware-software interaction, and possess strong analytical and debugging capabilities. Success in this role requires strong communication skills, attention to detail, and the ability to work effectively across multiple engineering disciplines. The candidate should be comfortable driving technical initiatives, influencing design decisions, and balancing performance, power, area, and quality objectives throughout the development process.

KEY RESPONSIBILITIES:

• Define and develop microarchitecture solutions for processor clocking, reset, and power management IP used in next-generation AMD CPUs.
• Collaborate with cross-functional architecture, RTL design, verification, physical design, and firmware teams to integrate and optimize power management features.
• Author microarchitecture specifications, interface definitions, and supporting technical documentation.
• Develop high-quality RTL using Verilog/SystemVerilog and contribute to firmware development in C/C++ for initialization, configuration, and control flows.
• Drive design quality through lint, CDC analysis, verification planning, debugging, and design review activities.
• During the first several months, gain familiarity with AMD's CPU architecture, power management framework, development flows, and existing IP infrastructure.
• Within the first year, take ownership of key architectural and implementation initiatives, delivering features that contribute directly to next-generation Ryzen, Threadripper, and EPYC processors.
• Support silicon validation, debug, and product bring-up activities while identifying opportunities for continuous improvement across design methodologies and workflows.

PREFERRED EXPERIENCE:

• Experience developing microarchitecture and RTL for processors, SoCs, or complex IP blocks.
• Strong Verilog/SystemVerilog design expertise.
• Experience developing embedded software or firmware in C/C++.
• Knowledge of digital design fundamentals including synchronous and asynchronous design concepts, clock domain crossing methodologies, and power-aware design techniques.
• Experience with low-power design strategies such as clock gating, power gating, DVFS, and multi-voltage domain implementation.
• Understanding processor power management architectures, including performance and power optimization techniques.
• Knowledge of hardware and firmware interactions related to power sequencing, control, and system-level flows.
• Experience with clock distribution, reset architecture, power management, thermal management, and reliability considerations in advanced SoCs.
• Familiarity with design-for-debug, design-for-test methodologies, and silicon validation activities.
• Strong debugging, problem-solving, communication, and collaboration skills.

ACADEMIC CREDENTIALS:

• Master's degree preferred in Electrical Engineering, Electrical and Computer Engineering, Computer Engineering, Computer Science, or a related technical field.

This role is not eligible for visa sponsorship.

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Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's "Responsible AI Policy" is available here.

This posting is for an existing vacancy.